IBM on Thursday unveiled a semiconductor architecture it calls NanoStack that packs nearly 100 billion transistors onto a chip the size of a fingernail, a density the Armonk, New York, company described as the equivalent of a 0.7-nanometer node and the first known chip technology below 1 nanometer.

The disclosure pushes the industry's atomic-scale yardstick past the 2-nanometer chips Taiwan Semiconductor Manufacturing Co. began producing this year and sets a target for Samsung, Intel and TSMC's own 1.4-nanometer effort, which the Taiwanese foundry has aimed at mass production around 2028. IBM does not make chips itself; it licenses its designs, currently to Japan's Rapidus, and said it sees a path to production within five years.

What is new

NanoStack layers sheets of transistors on top of one another instead of arranging them in a single plane. IBM said its prototype delivered up to 50 percent more performance, or 70 percent greater energy efficiency, than the company's 2-nanometer node, and a 40 percent improvement in SRAM, the short-term memory built into processors. Huiming Bu, IBM's vice president of semiconductors, told CBS News the SRAM gain was "something that we haven't seen in decades."

The nanometer figure no longer describes a physical dimension. It is an industry shorthand for transistor density, and the new design roughly doubles the count of IBM's 2-nanometer chip on the same footprint. More transistors mean faster processors and, the company argues, lower power draw per calculation, a metric that has moved to the center of the chip business as data centers compete for electricity to train and run artificial-intelligence models.

The block-of-flats analogy

Jay Gambetta, director of IBM Research, called the work a "landmark moment" for computing and said in a statement that "With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency."

Alan Woodward, a computer scientist at Surrey University, told the BBC the contrast with rival 3D approaches was one of ambition. "IBM's NanoStack is like proposing a 100-story skyscraper," he said, adding that Samsung and Intel are closer to 30- to 50-story buildings with their own stacking work. Woodward said IBM's proposals are "the most ambitious" in the field.

The engineering problem

Stacking transistors compounds two old chip-design headaches. Heat rises through the layers, and the insulating material between stacked sheets has to be thin enough to keep the device compact but thick enough that transistors switch off when they are told to. Leakage at those scales can stop a chip from working at all.

IBM acknowledged the production timeline carries its own risks. Building 0.7-nanometer-equivalent chips at scale requires advanced lithography equipment, fabrication expertise and capital expenditure measured in the billions of dollars, infrastructure controlled by a small number of foundries.

Caveat

IBM made similar claims for its 2-nanometer prototype in 2021, saying at the time the technology would also deliver large gains in performance and energy efficiency. Those chips have only this year reached mass production at TSMC, five years after the unveiling. The company has not said which customer would first license NanoStack, and no foundry has committed to building it.

The next public milestones are TSMC's 1.4-nanometer ramp targeted for 2028 and IBM's continued work with Rapidus on the 2-nanometer node Tokyo is trying to commercialize.